This is the last part of the series dedicated to the boost converter, where we walk through the PCB layout for a medium power boost with a synchronous MOSFET at the output instead of the more traditional output diode. You don’t have to read sections 5-1 or 5-2 first to appreciate this part, but I do recommend it.
PCB Layout for a DC-DC Boost Converter
A realistic schematic
Boost current loop analysis
The switch node goes first
The output capacitors
The input capacitors
Noisy and quiet sides of the control IC
Gate drives
Current sense lines
Power planes and four-layer treatment
In the following we’ll look at a realistic schematic for boost with all the components you haven’t seen in any of the simplified idealized schematics so far. I highly encourage all viewers to watch sections 3-1 and 3-2 of this webinar series before watching this one. These two parts present the theory behind PCB design for switchers. What follows is an analysis of the paths taken by the heavy currents into boost converter during its two switching states. Then the switch node, the output capacitors, the input capacitors and the control IC are placed in that order. Gate drives for the power FETs differential current sense lines and then the flooding of unused areas with power planes follow. The last part of section 5-3 explains how to take advantage of four-layer PCBs.
There is both art and science to PCB Layout. My goal is to convert you, my viewers, into electron whispers, or electron psychologists. Once you know why electrons do what they do, you’re well equipped to make them go where you want them to go, and that’s what PCB Design is all about.
Here’s the schematic for the circuit we’re going to layout. For a portable device it can put out a pretty decent amount of power, a peak of 30 Watts. The switching frequency is higher than usual, because this circuit needs to fit inside the handle of light saber. That’s right when I’m not designing power supplies, I spend my time defending peace and justice in the galaxy. The input to the circuit is two, 18, 600 sized lithium ion batteries. I break open the battery packs whenever a laptop computer dies and carefully, very carefully, save the batteries.
On more than one occasion the batteries caught on fire, which is why I officially recommend against doing this. Always buy properly designed battery packs with safety circuits. Power efficiency was a key for this design. So I used the synchronous bot controller. I probably gained around five percent efficiency by using the output MOSFET instead of a diode. Also included are two elements for switching edge control, which are a resistor in series with a boot strap pin to control the output MOSFET and a resistor in series with the gate of the control MOSFET. I start with zero ohm jumpers in these positions. Please see part four of this webinar series for lots of detail on this topic.
Every time you lay out a circuit board for a given topology, I recommend going through this current loop analysis. When doing so, I suggest including the input capacitors, which are sometimes omitted since they supply the AC portion of the input current, and its AC current that produces electrical noise.
When the control MOSFET is on the current, in blue, flows from the input and the input capacitor and flows through the boost inductor, causing the magnetic field to develop in storing energy. During this time the output capacitor is also hard at work, supplying all of the load current. When the control FET turns off the voltage across the inductor begins to rise. Remember that it’s capable, in theory, of going to infinity volts to maintain a constant current. Fortunately, it doesn’t have to go to infinity. As soon as the inductor voltage exceeds V out by more than a diode drop, the output diode forward biases. The current continues through the load, recharges the output capacitor and comes back to the source.
Now, let’s look at the circuit with both current loops. Any path with just one color is where heavy switched current flows. That means fast edges and high EMI. Naturally the MOSFET and diode are heavy switched currents, but the segment I want to draw attention to is the portion of ground that goes from the negative of the output capacitor back to the source the control FET. This part requires extra special attention.
One more thing before I move on. See how the current in the output capacitor reverses direction? That’s a clear indication that the output capacitor has suffered from heavy RMS ripple currents.
When doing this presentation I used to refer to this area in green as a loop, but someone raised their hand during a presentation one time and said the current never flows in this path. And they were right. It’s the area enclosed by the two power switches and the output capacitor that needs to be minimized. That minimizes the inductance of the partial paths taken by current through the two power tches. And the lower the inductance, the lower the noise, both conducted and radiated.
Here’s a trick that’s not obvious but works very well. Even if you have a nice solid ground plane on the bottom layer, or on an internal layer, or both, don’t use those layers to connect the negative of the output capacitor back to the source of the MOSFET. Instead, use a big fat trace or copper shape on the same layer as the components. That’s usually the top layer. When you do connect to ground planes in other layers put the vias next to the negative terminal of the output capacitor. That way, the output capacitor, or capacitors can filter as much of the high frequency noise as possible before I get into the ground plane and contaminates everything.
I always start by placing the inductor and the two power switches. Here, Q4 is the low side control MOSFET and Q3 is the high side output MOSFET, both are QFN style power packages measuring 3×3 mm.
The big coper areas with four fingers are the drains where the majority of the heat escapes the packages. Q3 has it easy because it’s drain connects to the V-Out node and that will have nice, big copper areas to dissipate heat. Q4 is the big challenge, probably the biggest of the whole design because it’s drain and power pad connect to the switch node. On the one hand, you want to keep the area of the switch node to a minimum because both voltage and the current move up and down very quickly making this an antennae. Big antennae radiate more and we definitely do not want to hear the song this antennae is broadcasting over FM. I typically place a solid shape that just covers the pad of L1, the source of Q3, and the drain of Q4, but if the switch node copper area is too small, then Q4 will overheat. This can happen easily in boost converters because the control FET has the highest peak and RMS currents plus lots of switching loss. It’s a perfect storm for cooked MOSFETS.
This is the last part of the series dedicated to the boost converter, where we walk through the PCB layout for a medium power boost with a synchronous MOSFET at the output instead of the more traditional output diode. You don’t have to read sections 5-1 or 5-2 first to appreciate this part, but I do recommend it.
PCB Layout for a DC-DC Boost Converter
A realistic schematic
Boost current loop analysis
The switch node goes first
The output capacitors
The input capacitors
Noisy and quiet sides of the control IC
Gate drives
Current sense lines
Power planes and four-layer treatment
In the following we’ll look at a realistic schematic for boost with all the components you haven’t seen in any of the simplified idealized schematics so far. I highly encourage all viewers to watch sections 3-1 and 3-2 of this webinar series before watching this one. These two parts present the theory behind PCB design for switchers. What follows is an analysis of the paths taken by the heavy currents into boost converter during its two switching states. Then the switch node, the output capacitors, the input capacitors and the control IC are placed in that order. Gate drives for the power FETs differential current sense lines and then the flooding of unused areas with power planes follow. The last part of section 5-3 explains how to take advantage of four-layer PCBs.
There is both art and science to PCB Layout. My goal is to convert you, my viewers, into electron whispers, or electron psychologists. Once you know why electrons do what they do, you’re well equipped to make them go where you want them to go, and that’s what PCB Design is all about.
Here’s the schematic for the circuit we’re going to layout. For a portable device it can put out a pretty decent amount of power, a peak of 30 Watts. The switching frequency is higher than usual, because this circuit needs to fit inside the handle of light saber. That’s right when I’m not designing power supplies, I spend my time defending peace and justice in the galaxy. The input to the circuit is two, 18, 600 sized lithium ion batteries. I break open the battery packs whenever a laptop computer dies and carefully, very carefully, save the batteries.
On more than one occasion the batteries caught on fire, which is why I officially recommend against doing this. Always buy properly designed battery packs with safety circuits. Power efficiency was a key for this design. So I used the synchronous bot controller. I probably gained around five percent efficiency by using the output MOSFET instead of a diode. Also included are two elements for switching edge control, which are a resistor in series with a boot strap pin to control the output MOSFET and a resistor in series with the gate of the control MOSFET. I start with zero ohm jumpers in these positions. Please see part four of this webinar series for lots of detail on this topic.
Every time you lay out a circuit board for a given topology, I recommend going through this current loop analysis. When doing so, I suggest including the input capacitors, which are sometimes omitted since they supply the AC portion of the input current, and its AC current that produces electrical noise.
When the control MOSFET is on the current, in blue, flows from the input and the input capacitor and flows through the boost inductor, causing the magnetic field to develop in storing energy. During this time the output capacitor is also hard at work, supplying all of the load current. When the control FET turns off the voltage across the inductor begins to rise. Remember that it’s capable, in theory, of going to infinity volts to maintain a constant current. Fortunately, it doesn’t have to go to infinity. As soon as the inductor voltage exceeds V out by more than a diode drop, the output diode forward biases. The current continues through the load, recharges the output capacitor and comes back to the source.
Now, let’s look at the circuit with both current loops. Any path with just one color is where heavy switched current flows. That means fast edges and high EMI. Naturally the MOSFET and diode are heavy switched currents, but the segment I want to draw attention to is the portion of ground that goes from the negative of the output capacitor back to the source the control FET. This part requires extra special attention.
One more thing before I move on. See how the current in the output capacitor reverses direction? That’s a clear indication that the output capacitor has suffered from heavy RMS ripple currents.
When doing this presentation I used to refer to this area in green as a loop, but someone raised their hand during a presentation one time and said the current never flows in this path. And they were right. It’s the area enclosed by the two power switches and the output capacitor that needs to be minimized. That minimizes the inductance of the partial paths taken by current through the two power tches. And the lower the inductance, the lower the noise, both conducted and radiated.
Here’s a trick that’s not obvious but works very well. Even if you have a nice solid ground plane on the bottom layer, or on an internal layer, or both, don’t use those layers to connect the negative of the output capacitor back to the source of the MOSFET. Instead, use a big fat trace or copper shape on the same layer as the components. That’s usually the top layer. When you do connect to ground planes in other layers put the vias next to the negative terminal of the output capacitor. That way, the output capacitor, or capacitors can filter as much of the high frequency noise as possible before I get into the ground plane and contaminates everything.
I always start by placing the inductor and the two power switches. Here, Q4 is the low side control MOSFET and Q3 is the high side output MOSFET, both are QFN style power packages measuring 3×3 mm.
The big coper areas with four fingers are the drains where the majority of the heat escapes the packages. Q3 has it easy because it’s drain connects to the V-Out node and that will have nice, big copper areas to dissipate heat. Q4 is the big challenge, probably the biggest of the whole design because it’s drain and power pad connect to the switch node. On the one hand, you want to keep the area of the switch node to a minimum because both voltage and the current move up and down very quickly making this an antennae. Big antennae radiate more and we definitely do not want to hear the song this antennae is broadcasting over FM. I typically place a solid shape that just covers the pad of L1, the source of Q3, and the drain of Q4, but if the switch node copper area is too small, then Q4 will overheat. This can happen easily in boost converters because the control FET has the highest peak and RMS currents plus lots of switching loss. It’s a perfect storm for cooked MOSFETS.
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